1. Field of the Invention
The present invention relates generally to a high-speed encoder, and more particularly, to a high-speed encoder used in an analog-to-digital converter.
2. Description of the Related Art
Analog-to-digital (A/D) converters are circuits, which convert an analog signal to a digital signal. With an increase in demand for mixed-mode systems such as household electrical appliances, the need for A/D converters has also increased. Consequently, manufacturers of systems requiring a high-speed operation, such as a digital video disc (DVD) player, a direct broadcasting for satellite (DBS) receiver, other communication application products, or the like, desire a technique for making an A/D converter into a chip using a CMOS process to keep manufacturing costs low. Due to this desire for low cost CMOS processing, a technique for directly processing a radio frequency (RF) signal raises additional issues. For example, a CMOS A/D converter for processing a high-speed signal such as the RF signal must be capable of a conversion speed of 1 giga sample per second (GSPS) or more and have the characteristics of a medium resolution.
A full-flash A/D converter is suitable for a high-speed operation in a range of GHz. A conventional full-flash A/D converter includes a comparator array, which converts an analog signal into a digital code referred to as a thermometer code, a NAND array, which converts the thermometer code into a 1-of-n code, and a binary encoder block, which converts the 1-of-n code into a final binary code.
Various implementations of realizing the binary encoder block include an implementation using a logic tree and an implementation using a ROM structure. In the implementation using the logic tree, a large amount of power is consumed and timing errors can easily occur. For example, in the event that the binary encoder block is realized using a 2-input logic circuit, 69 logic circuits are needed to make 1 bit of the final binary code. Also, the propagation of the numerous stages of logic circuits causes delays in transmitting a synchronous signal. As a result, an additional circuit, such as a flip-flop or the like, is required.
On the other hand, an encoder using a ROM structure occupies a smaller area and consumes a smaller amount of power. There is also less occurrences of timing errors. Thus, the encoder using a ROM is generally used in applications requiring a conversion speed of 100 MHz or higher. However, for a conversion speed of 1 GHz, it is difficult for an encoder using the ROM structure to convert a signal within 1 cycle.
A need therefore exists for a binary encoder, which occupies a small area and uses a small amount of power, and is capable of a fast conversion speed of several tens or more of GHz.